Synclink Was Critical To SDRam Development


Posted on 15th October 2015 by admin in RAM |Tech

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With Synclink, packet-oriented transactions between the controller and the modules would take place over semi-synchronous, unidirectional buses. Commands would move on one bus and responses on a second, at speeds as high as 500 Mbytes/s.

The proposal contained ideas about bus structures and signaling techniques that have not yet been approved by the Synclink working group. But the group does appear in agreement that the new interface will be based on a Ramlink-like protocol. A command burst in the protocol would contain an address, a transaction code that specified the operation to be performed, and a time at which a response should be returned to the memory controller. Thus, a memory-read operation might consist of a read address, a transaction code specifying that 64 consecutive bytes should be read, and a time stamp indicating that the results should be returned starting in exactly 25 clock cycles.

The memory controller would create the command burst, including figuring out how long the transaction will take, and scheduling the return of data on the bus. Thus, much of the logic needed for memory-system timing would remain in the controller, where it would not affect the complexity or cost of the DRAM chips.

In Wiggers’s proposal, the commands would travel from the controller to the memory array over an 8-bit upper bus. That bus could carry a new command byte every 2 ns. It would not be exactly synchronous, in that a strobe pulse would travel along the bus lines with the command information.

The upper bus would be unidirectional, eliminating the overhead of arbitrating for the bus or turning it around. Thus, the whole 500-Mbyte/s bandwidth would be available for addresses, commands and other data. Responses from the memory system would be carried on a second, 16-bit bus with a 4-ns cycle time. Thus, data transfers would not share bandwidth with addresses or commands.

Hits 500 Mbytes/s

Since commands are split from responses by a time interval set in the controller, the memory system could be almost completely non-blocking. That is, numerous memory requests could be in process at once without forcing the memory system to wait for completion. In theory, then, transactions could deliver data to CPU caches at a sustained 500 Mbytes/s. In comparison, Rambus-arguably the fastest shipping technology-multiplexes addresses, commands and data on a single 500-Mbyte/s channel.

While the Synclink protocol appears well-grounded, questions of signaling and bus structure are up in the air. Wiggers will present his ideas to the working group as an individual, not as an official HP representative. The working group must consider the proposal in the context of controversy over memory-system electrical standards and market realities.

“Issues like bus width, bus frequency and signaling are still not determined,” warned one group member. He pointed out that the signaling standards that would permit 2-ns operation are a particularly hot topic.

“Jedec standardized Gunning Transceiver Logic [GTL] and Center-Tap Transceiver Logic [CTT],” the designer observed. “But then people objected to the power required by those interfaces, and so Jedec went back and standardized High-Speed Transceiver Logic (HSTL). Then, it used HSTL to define the new Jedec SDRAM module.

“But now we have simulations that show HSTL has insufficient signal swing to pull the signal out of the noise in a module environment,” he said.

“So, Jedec is taking a hard look at a proposal Fujitsu engineers made some time ago for a Stub-Terminated Bus (STB). The concept is like CTT, except that you put 5-OHM to 10-OHM resistors on the outputs. Simulations seem to confirm that STB would work at the required frequency in a module environment for Synclink.”

EDO skeptics

The uncertainty is keeping memory vendors up nights. Extended data out (EDO) DRAMs are just meeting wide customer acceptance, and a minor tweak-burst EDO DRAMs-is facing skepticism. Advanced ideas like SDRAMs and Rambus DRAMs are not widely used, though design wins for the new architectures at Sega and Nintendo might speed market acceptance.

All these technologies except Rambus are still based on low-voltage TTL signaling. “People see their way clear to 66- or 75-MHz bus frequencies with low-voltage-TTL (LVTTL) EDO DRAMs,” observed Micron Technologies strategic marketing manager Jeff Mailloux. “Just where LVTTL runs out of steam depends on the number of memory modules, the layout and so forth. But it is very hard to see LVTTL running above 100 MHz.

“Above that frequency, we may see existing architectures like burst EDO or SDRAM, but with a new signaling standard. It isn’t clear that even SDRAM can do things that burst EDO can’t do. It is even less clear that systems designers will accept the latency you incur when you move to a packet-oriented bus like Rambus or Synclink. But, clearly, the demand for something is out there.”

That demand is fueling ideas. Many individual engineers have put together signaling and bus designs. And design teams are burning the simulator cycles at both ends inside systems houses and DRAM vendors. But, today, Synclink may be in a unique position in that it has direct involvement from DRAM companies, including Hyundai and Micron.

Though DRAM vendors are expressing some concerns, Wiggers remains optimistic: “Nothing is final, but something is finally becoming tangible.”

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