Synclink Was Critical To SDRam Development


Posted on 15th October 2015 by admin in RAM |Tech

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With Synclink, packet-oriented transactions between the controller and the modules would take place over semi-synchronous, unidirectional buses. Commands would move on one bus and responses on a second, at speeds as high as 500 Mbytes/s.

The proposal contained ideas about bus structures and signaling techniques that have not yet been approved by the Synclink working group. But the group does appear in agreement that the new interface will be based on a Ramlink-like protocol. A command burst in the protocol would contain an address, a transaction code that specified the operation to be performed, and a time at which a response should be returned to the memory controller. Thus, a memory-read operation might consist of a read address, a transaction code specifying that 64 consecutive bytes should be read, and a time stamp …